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s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 1 - product list ................................................................................................................................................................... 3 description .................................................................................................................................................................... 3 ordering information ..................................................................................................................................................... 3 features ........................................................................................................................................................................ 3 pin configuration .......................................................................................................................................................... 3 block diagram ............................................................................................................................................................... 6 special function register (sfr) .................................................................................................................................. 8 function description ................................................................................................................................................... 10 1. general features ........................................................................................................................................... 10 1.1 embedded flash ................................................................................................................................... 10 1.2 io pads ................................................................................................................................................. 10 1.3 system control register (sconf) ....................................................................................................... 10 2. instruction set ................................................................................................................................................ 11 3. memory structure .......................................................................................................................................... 15 3.1 program memory .................................................................................................................................. 15 3.2 data memory ......................................................................................................................................... 16 3.3 data memory - lower 128 byte (00h to 7fh) ......................................................................................... 16 3.4 data memory - higher 128 byte (80h to ffh) ........................................................................................ 16 4. cpu engine ................................................................................................................................................... 17 4.1 accumulator .......................................................................................................................................... 17 4.2 b register ............................................................................................................................................. 17 4.3 program status word ............................................................................................................................ 18 4.4 stack pointer ......................................................................................................................................... 18 4.5 data pointer .......................................................................................................................................... 18 5. gpio .............................................................................................................................................................. 19 6. timer 0 and timer 1 ....................................................................................................................................... 20 6.1 timer/counter mode control register (tmod) ....................................................................................... 20 6.2 timer/counter control register (tcon) ................................................................................................. 21 6.3 mode 0 (13 - bit counter/timer) .............................................................................................................. 21 6.4 mode 1 (16 - bit counter/timer) .............................................................................................................. 22 6.5 mode 2 (8 - bit auto - reload counter/timer) ............................................................................................ 22 6.6 mode 3 (timer 0 acts as two independent 8 bit timers / counters) ..................................................... 22 7. timer 2 ........................................................................................................................................................... 24 7.1 capture mode ....................................................................................................................................... 25 7.2 auto - reload (up or down counter) ....................................................................................................... 26 7.3 programmable clock out ....................................................................................................................... 27 8. serial interface ? uart ................................................................................................................................. 29 8.1 serial interface ...................................................................................................................................... 29 8.1.1 mode 0 .......................................................................................................................................... 30 8.1.2 mode 1 .......................................................................................................................................... 30 8.1.3 mode 2 .......................................................................................................................................... 31 8.1.4 mode 3 .......................................................................................................................................... 31 8.2 multiprocessor communication of serial interface ............................................................................... 31 8.3 baud rate generator ............................................................................................................................ 32 8.3.1 serial interface mode 0 ................................................................................................................ 32 8.3.2 serial interface mode 2 ................................................................................................................ 32 8.3.3 serial interface mode 1 and 3 ...................................................................................................... 32 9. interrupt .......................................................................................................................................................... 33 10. watch dog timer ........................................................................................................................................... 35 11. power management unit ............................................................................................................................... 37 11.1 idle mode .............................................................................................................................................. 37 11.2 power down mode ................................................................................................................................ 37 12. in - system programming (internal isp) .......................................................................................................... 38 12.1 isp service program .............................................................................................................................. 38 12.2 lock bit (n) ........................................................................................................................................... 38 12.3 program the isp service program ........................................................................................................ 39
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 2 - 12.4 initiate isp service program ................................................................................................................. 39 12.5 isp register ? ispfah, ispfal, ispfd and ispc ............................................................................... 39 operating conditions .................................................................................................................................................. 42 dc characteristics ...................................................................................................................................................... 42
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 3 - product list sm 595 3 w40pp , SM5953 w44 j p , SM5953 w44qp, description the sm 595 3 series pr oduct is an 8 - bit single chip micro controller with 15 k b flash & 256 byte s s ram embedded. it has in - system programming (isp) function and is a derivative of the 8052 micro controller family. sm 5953 is a versatile and cost effective controller for those applications which demand up to 32 i/o pins, or applications which need up to 15 k byte flash memory either for program or for data or mixed. to program the on - chip flash memory, a commercial writer is available to do it in parallel programming method. the on - chip flash memory can be programmed in either parallel or serial interface with its isp feature. ordering information sm 5953 ihhkl yww i: process identifier { w = 2 . 4 v ~ 5.5v} hh: pin count k: package type postfix {as table below } l:pb free identifier {no text is non - pb f ree ?p? is pb free} y : year ww : week postfix package p pdip j plcc q pqfp features ? main flash rom 15k b ? working voltage 2 . 4 v~5.5v runs up to 40mhz ? general 8052 family compatible with 12 clocks in one machine cycle ? 6 clocks in one machine cycle is a lso supported ? 256 bytes sram as standard 8052 . ? 16- bit data pointers (dptr). ? one serial peripheral interfaces in full duplex mode (uart). - synchronous mode, fixed baud rate. - 8 - bit uart mode, variable baud rate. - 9 - bit uart mode, fixed baud rate. - 9 - bit uart mo de, variable baud rate. ? three 16 - bit timer/counters. (timer 0, 1, 2). ? one watch dog timer (wdt) . ? isp/iap functions. ? isp service program space configurable in n (n=0 to 8). ? eeprom function. ? six interrupt sources with two priority levels. ? four 8 - bit i/o port s ? io pad esd over 4kv ? enhance user code protection. ? power management unit for idle and power down modes.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 3 - pin configuration 40 pin p dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 t2/p1.0 t2ex/p1.1 p1.2 vdd p1.3 p1.4 p1.5 p1.6 p1.7 reset rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 vss p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 SM5953ihhpp yww (40l pdip top view)
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 4 - 44 pin p lcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 30 29 40 41 42 43 44 p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 nc p1.5 p1.6 p1.7 reset rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3 .3 t0/p3.4 t1/p3.5 nc wr/p3.6 rd/p3.7 xtal2 xtal1 vss nc a12/p2.4 a11/p2.3 a10/p2.2 a9/p2.1 a8/p2.0 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale psen p2.7/a15 p2.6/a14 p2.5/a13 nc vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 SM5953 ihhjp yww (44l plcc top view )
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 5 - 44 pin p qfp t2/p1.0 t2ex/p1.1 p1.2 p1.3 p1.4 nc p1.5 p1.6 p1.7 reset rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 nc p3.6/wr p3.7/rd xtal2 xtal1 vss nc p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale psen p2.7/a15 p2.6/a14 p2.5/a13 nc vdd ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 1 2 3 4 5 6 7 8 9 10 11 13 14 15 12 22 21 20 19 18 17 16 24 23 33 32 31 30 29 28 27 26 25 43 44 34 35 36 38 39 40 41 42 37 SM5953 ihhqp yww (44l pqfp top view)
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 6 - block diagram uart flash 8kbytes sram 256bytes interrupt timer 0/1 timer2 isp port 0 port 1 port 2 port 3 port 0 port 1 port 2 port 3 t0 t1 t2 t2ex rxd txd interface control xtal1 xtal2 cpu rxd txd reset circuit reset ea psen ale wdt
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 7 - pin description 40 l pdip 40 l plcc 40 l pqfp symbol i/o description 1 2 40 p1.0/t2 i/o bit 0 of port 1 & timer 2 external input clock 2 3 41 p1.1/t2ex i/o bit 1 of port 1 & timer 2 captur e trigger 3 4 42 p1.2 i/o bit 2 of port 1 4 5 43 p1.3 i/o bit 3 of port 1 5 6 44 p1.4 i/o bit 4 of port 1 6 7 1 p1.5 i/o bit 5 of port 1 7 8 2 p1.6 i/o bit 6 of port 1 8 9 3 p1.7 i/o bit 7 of port 1 9 10 4 reset i reset pin 10 11 5 p3.0/rxd i/o bit 0 of port 3 & serial interface channel receive data 11 13 7 p3.1/txd i/o bit 1 of port 3 & serial interface channel transmit data 12 14 8 p3.2 /int0 i/o bit 2 of port 3 & interrupt 0 13 15 9 p3.3/ int1 i/o bit 3 of port 3 & interrupt 1 14 16 10 p3.4 /t0 i/o bit 4 of port 3 & timer 0 external input 15 17 11 p3.5/ t1 i/o bit 5 of port 3 & timer 1 external input 16 18 12 p3.6/ wr i/o bit 6 of port 3 & external memory write 17 19 13 p3. 7 / rd i/o bit 7 of port 3 & external memory read 18 20 14 xtal2 i /o crystal output 19 21 15 xtal1 i/o crystal input 20 22 16 vss i ground 21 24 18 p2.0/a8 i/o bit 0 of port 2 & bit 8 of external memory address 22 25 19 p2.1/a9 i/o bit 1 of port 2 & bit 9 of external memory address 23 26 20 p2.2/a10 i/o bit 2 of por t 2 & bit 10 of external memory address 24 27 21 p2.3/a11 i/o bit 3 of port 2 & bit 11 of external memory address 25 28 22 p2.4/ a12 i/o bit 4 of port 2 & bit 12 of external memory address 26 29 23 p2.5/ a13 i/o bit 5 of port 2 & bit 13 of external memory address 27 30 24 p2.6/ a14 i/o bit 6 of port 2 & bit 14 of external memory address 28 31 25 p2. 7 / a15 i/o bit 7 of port 2 & bit 15 of external memory address 29 32 26 psen o program storage enable 30 33 27 ale o address latch enable 31 35 29 ea i exter nal access 32 36 30 p0.7/ ad7 i/o bit 7 of port 0 & data/address bit 7 of external memory 33 37 31 p0. 6 / ad6 i/o bit 6 of port 0 & data/address bit 6 of external memory 34 38 32 p0.5/ ad5 i/o bit 5 of port 0 & data/address bit 5 of external memory 35 39 3 3 p0.4/ ad4 i/o bit 4 of port 0 & data/address bit 4 of external memory 36 40 34 p0.3/ ad3 i/o bit 3 of port 0 & data/address bit 3 of external memory 37 41 35 p0.2/ ad2 i/o bit 2 of port 0 & data/address bit 2 of external memory 38 42 36 p0.1/ ad1 i/o bit 1 of port 0 & data/address bit 1 of external memory 39 43 37 p0.0/ ad0 i/o bit 0 of port 0 & data/address bit 0 of external memory 40 44 38 vdd i power supply
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 8 - special function register (sfr) a map of the special function registers is shown as below: hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex f8 ff f0 b ispfah ispfal ispfd ispc f7 e8 ef e0 acc e7 d8 df d0 psw d7 c8 t2con t2mod rc ap2 l rcap2 h tl2 th2 cf c0 c7 b8 i p sconf bf b 0 p3 b7 a8 ie af a0 p2 a7 98 scon sbuf wdtc 9f 90 p1 97 88 tcon tmod tl0 tl1 th0 th1 8f 80 p0 sp dpl dph pcon 87 hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 9 - note: special function registers reset values and description for sm 5953. register location reset value description 1 p0 80h ffh port 0 2 sp 81h 07h stack pointer 3 dpl 82h 00h data pointer 0 low byte 4 dph 83h 00h data pointer 0 high byte 5 pcon 87h 0 0h power control 6 tcon 88h 00h ti mer/counter control 7 tmod 89h 00h timer mode control 8 tl0 8ah 00h timer 0, low byte 9 tl1 8bh 00h timer 1, low byte 10 th0 8ch 00h timer 0, high byte 11 th1 8dh 00h timer 1, high byte 12 p1 90h ffh port 1 13 scon 98h 00h serial port 0, control reg ister 14 sbuf 99h 00h serial port 0, data buffer 16 p2 a0h ffh port 2 17 ie a8h 00h interrupt enable 18 p3 b0h ffh port 3 19 ip b8h 00h interrupt priority 20 sconf bfh 0 2 h system control register 21 t2con c8h 00h timer 2 control 22 t2mod c9h 00h ti mer 2 mode 23 rcap2l cah 00h timer2 capture low 24 rcap2h cbh 00h timer2 capture high 25 tl2 cch 00h timer 2, low byte 26 th2 cdh 00h timer 2, high byte 27 psw d0h 00h program status word 28 acc e0h 00h accumulator 29 b f0h 00h b register 30 i spfah f4h 00h isp flash address - high register 31 ispfal f5h 00h isp flash address - low register 32 ispfd f6h 00h isp flash data register 33 isp c f7h 00h isp control register
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 10 - function description 1. general features sm 5953 is an 8 - bit micro - controller. a ll of its functions and the detailed meanings of sfr will be given in the following sections. 1.1 embedded flash the program can be loaded into the embedded 15 k b flash memory via its writer or in - system programming (isp). the high - quality flash suitable for r e - programming and data recording as eeprom. 1.2 io pads the sm 5953 has f ive i/o ports: port 0, port 1, port 2 , port 3 . port 0 ~ port 3 are 8 - bit ports . these are: quasi - bidirectional (standard 8051 port outputs) with port 1~ 3 , and open drain with port 0 . all th e pads are with slew rate to reduce emi. the io pads can withstand esd in human body mode guaranteeing the sm 5953 ?s quality in high electro - static environments. 1.3 system control register (sconf ) mnemonic: sconf address: bfh 7 6 5 4 3 2 1 0 reset wdr - - - - ispe - alei 00h wdr watch dog timer reset. when system reset by watch dog timer overflow, wdr will be set to 1. user should check wdr bit whenever un - predicted reset happened. ispe isp function enable bit. when enable the isp function, ispe wil l be set to 1. alei ale output inhibit bit. when default, it can inhibit the clock signal in (fosc/6) hz output to the ale pin. when set to 1, the ale pin output will stop to reduce emi.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 11 - 2. instruction set a ll sm 5953 instructions are binary code compati ble and perform the same functions as they do with the industry standard 8051. the following tables give a summary of the instruction set cycles of the sm 5953 microcontroller core. as given in table table 2 - 1 : arithmetic operations mnemonic description code bytes cycles add a,rn add register to accumulator 28- 2f 1 1 add a,direct add direct byte to accumulator 25 2 1 add a,@ri add indirect ram to accumulator 26- 27 1 1 add a,#data add immediate data to accum ulator 24 2 1 addc a,rn add register to accumulator with carry flag 38- 3f 1 1 addc a,direct add direct byte to a with carry flag 35 2 1 addc a,@ri add indirect ram to a with carry flag 36- 37 1 1 addc a,#data add immediate data to a with carry flag 34 2 1 subb a,rn subtract register from a with borrow 98- 9f 1 1 subb a,direct subtract direct byte from a with borrow 95 2 1 subb a,@ri subtract indirect ram from a with borrow 96- 97 1 1 subb a,#data subtract immediate data from a with borrow 94 2 1 inc a increment accumulator 04 1 1 inc rn increment register 08- 0f 1 1 inc direct increment direct byte 05 2 1 inc @ri increment indirect ram 06- 07 1 1 inc dptr increment data pointer a3 1 2 dec a decrement accumulator 14 1 1 dec rn decrement register 18- 1f 1 1 dec direct decrement direct byte 15 2 1 dec @ri decrement indirect ram 16- 17 1 1 mul ab multiply a and b a4 1 4 div divide a by b 84 1 4 da a decimal adjust accumulator d4 1 1
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 12 - table 2 - 2 : logic o perations mnemonic description code bytes cycles anl a,rn and register to accumulator 58- 5f 1 1 anl a,direct and direct byte to accumulator 55 2 1 anl a,@ri and indirect ram to accumulator 56- 57 1 1 anl a,#data and immediate data to accumulator 54 2 1 anl direct,a and accumulator to direct byte 52 2 1 anl direct,#data and immediate data to direct byte 53 3 2 orl a,rn or register to accumulator 48- 4f 1 1 orl a,direct or direct byte to accumulator 45 2 1 orl a,@ri or indirect ram to accumulator 46- 47 1 1 orl a,#data or immediate data to accumulator 44 2 1 orl direct,a or accumulator to direct byte 42 2 1 orl direct,#data or immediate data to direct byte 43 3 2 xrl a,rn exclusive or register to accumulator 68- 6f 1 1 xrl a,direct exclusive or direc t byte to accumulator 65 2 1 xrl a,@ri exclusive or indirect ram to accumulator 66- 67 1 1 xrl a,#data exclusive or immediate data to accumulator 64 2 1 xrl direct,a exclusive or accumulator to direct byte 62 2 1 xrl direct,#data exclusive or immediate data to direct byte 63 3 2 clr a clear accumulator e4 1 1 cpl a complement accumulator f4 1 1 rl a rotate accumulator left 23 1 1 rlc a rotate accumulator left through carry 33 1 1 rr a rotate accumulator right 03 1 1 rrc a rotate accumulator right t hrough carry 13 1 1 swap a swap nibbles within the accumulator c4 1 1
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 13 - table 2 - 3 : data transfer mnemonic description code bytes cycles mov a,rn move register to accumulator e8 - ef 1 1 mov a,direct move dir ect byte to accumulator e5 2 1 mov a,@ri move indirect ram to accumulator e6 - e7 1 1 mov a,#data move immediate data to accumulator 74 2 1 mov rn,a move accumulator to register f8 - ff 1 1 mov rn,direct move direct byte to register a8 - af 2 2 mov rn,#data move immediate data to register 78- 7f 2 1 mov direct,a move accumulator to direct byte f5 2 1 mov direct,rn move register to direct byte 88- 8f 2 2 mov direct1,direct2 move direct byte to direct byte 85 3 2 mov direct,@ri move indirect ram to direct by te 86- 87 2 2 mov direct,#data move immediate data to direct byte 75 3 2 mov @ri,a move accumulator to indirect ram f6 - f7 1 1 mov @ri,direct move direct byte to indirect ram a6 - a7 2 2 mov @ri,#data move immediate data to indirect ram 76- 77 2 1 mov dptr ,#data16 load data pointer with a 16 - bit constant 90 3 2 movx a,@ri move external ram (8 - bit addr.) to a e2 - e3 1 2 movx a,@dptr move external ram (16 - bit addr.) to a e0 1 2 movx @ri,a move a to external ram (8 - bit addr.) f2 - f3 1 2 movx @dptr,a move a t o external ram (16 - bit addr.) f0 1 2 movc a,@a+dptr move code byte relative to dptr to accumulator 93 1 2 movc a,@a+pc move code byte relative to pc to accumulator 83 1 2 push direct push direct byte onto stack c0 2 2 pop direct pop direct byte from st ack d0 2 2 xch a,rn exchange register with accumulator c8 - cf 1 1 xch a,direct exchange direct byte with accumulator c5 2 1 xch a,@ri exchange indirect ram with accumulator c6 - c7 1 1 xchd a,@ri exchange low - order nibble indir. ram with a d6 - d7 1 1
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 14 - ta ble 2 - 4 : program branches mnemonic description code bytes cycles acall addr11 absolute subroutine call xxx11 2 2 lcall addr16 long subroutine call 12 3 2 ret from subroutine 22 1 2 reti from interrupt 32 1 2 ajmp addr11 absolute jump xxx01 2 2 ljmp addr16 long iump 02 3 2 sjmp rel short jump (relative addr.) 80 2 2 jmp @a+dptr jump indirect relative to the dptr 73 1 2 jz rel jump if accumulator is zero 60 2 2 jnz rel jump if accumulator is not zero 70 2 2 jc rel jump if carry flag is set 40 2 2 jnc jump if carry flag is not set 50 2 2 jb bit,rel jump if direct bit is set 20 3 2 jnb bit,rel jump if direct bit is not set 30 3 2 jbc bit,direct rel jump if direct bit is set and clear bit 10 3 2 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 2 cjne a,#data rel compare immediate to a and jump if not equal b4 3 2 cjne rn,#data rel compare immed. to reg. and jump if not equal b8 - bf 3 2 cjne @ri,#data rel compare immed. to ind. an d jump if not equal b6 - b7 3 2 djnz rn,rel decrement register and jump if not zero d8 - df 2 2 djnz direct,rel decrement direct byte and jump if not zero d5 3 2 nop no operation 00 1 1 table 2 - 5 : boolean man ipulation mnemonic description code bytes cycles clr c clear carry flag c3 1 1 clr bit clear direct bit c2 2 1 setb c set carry flag d3 1 1 setb bit set direct bit d2 2 1 cpl c complement carry flag b3 1 1 cpl bit complement direct bit b2 2 1 anl c,bit and direct bit to carry flag 82 2 2 anl c,/bit and complement of direct bit to carry b0 2 2 orl c,bit or direct bit to carry flag 72 2 2 orl c,/bit or complement of direct bit to carry a0 2 2 mov c,bit move direct bit to carry flag a2 2 1 mov bit,c move carry flag to direct bit 92 2 2
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 15 - 3. memory structure the sm 5953 memory structure follows general 8052 structure. it is 15 k b program memory . 3.1 program memory the sm 5953 has 15 k b on - chip flash memory which can be used as general program memory or eeprom, on which include up to 3.875 k byte specific isp service program memory space. the address range for the 15 k byte is $0000 h to $ 3bff h . the address range for the isp service program is $ 3 0 00h to $ 3f7f h . the isp service program size can be partitioned as n blocks (n=0 to 8). when n = 1 means address $ 3 e0 0 h to $ 3 f 7 f h reserved for isp service program. when n=2 means memory address $ 3 c 00 h to $ 3 f 7 f h reserved for isp service program?etc. value n can be set and programmed into sm 5953 configuration by writer. as shown in fig. 3 - 1 . 3f7f 3e00 3c00 3a00 3800 3600 3400 3200 3000 0000 isp service program space, up to 3.875k 15k program memory space n=8 n=7 n=6 n=5 n=4 n=3 n=2 n=1 n=0 fig. 3 - 1 : sm 5953 programmable flash
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 16 - 3.2 data memory the sm 5953 has 256b on- chip sram . as shown in fig. 3 - 2 higher 128 bytes (accessed by indirect addressing mode only) lower 128 bytes (accessed by direct & indirect addressing mode ) sfr (accessed by direct addressing mode only) 00 7f 80 ff 80 ff fig. 3 - 2 : ram architecture 3.3 data memory - lower 128 byte (00h to 7fh) data memory 00h to ffh is the same as 8052. the address 00h t o 7fh can be accessed by direct and indirect addressing modes. address 00h to 1fh is register area. address 20h to 2fh is memory bit area. address 30h to 7fh is for general memory area. 3.4 data memory - higher 128 byte (80h to ffh) the address 80h to ffh can be accessed by indirect addressing mode. address 80h to ffh is data area.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 17 - 4. cpu engine the sm 5953 engine is composed of four components: (1) control unit (2) arithmetic ? logic unit (3) memory control unit (4) ram and sfr control unit the sm 5953 en gine allows to fetch instruction from program memory and to execute using ram or sfr. the following chapter describes the main engine register. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst 8051 core acc accumulator e0h a cc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00h b b register f0h b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h psw program status word d0h cy ac f0 rs[1:0] ov psw.1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 82h dpl[7:0] 00h dph data pointe r high 83h dph[7:0] 00h 4.1 accumulator acc is the accumulator register. most instructions use the accumulator to store the operand. mnemonic: acc address: e0h 7 6 5 4 3 2 1 0 reset acc.7 acc.6 acc05 acc.4 acc.3 acc.2 acc.1 acc.0 00h acc[7:0]: the a (or acc) register is the standard 8052 accumulator. 4.2 b register the b register is used during multiply and divide instructions. it can also be used as a scratch pad register to store temporary data. mnemonic: b address: f0h 7 6 5 4 3 2 1 0 reset b.7 b.6 b. 5 b.4 b.3 b.2 b.1 b.0 00h b[7:0]: the b register is the standard 8052 register that serves as a second accumulator.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 18 - 4.3 program status word mnemonic: psw address: d0h 7 6 5 4 3 2 1 0 reset cy ac f0 rs [1:0] ov f1 p 00h cy: carry flag. ac: auxiliary c arry flag for bcd operations. f0: general purpose flag 0 available for user. rs[1:0]: register bank select, used to select working register bank. rs[1:0] bank selected location 00 bank 0 00h ? 07h 01 bank 1 08h ? 0fh 10 bank 2 10h ? 17h 11 bank 3 18h ? 1fh ov: overflow flag. f1: general purpose flag 1 available for user. p: parity flag, affected by hardware to indicate odd/even number of ?one? bits in the accumulator, i.e. even parity. 4.4 stack pointer the stack pointer is a 1 - byte register initial ized to 07h after reset. this register is incremented before push and call instructions, causing the stack to start from location 08h. mnemonic: sp address: 81h 7 6 5 4 3 2 1 0 reset sp [7:0] 07h sp[7:0]: the stack pointer stores the scratchpad ram a ddress where the stack begins. in other words, it always points to the top of the stack. 4.5 data pointer the data pointer (dptr) is 2 - bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2 - byte register (e.g. mov dptr, #data16) o r as two separate registers (e.g. mov dpl,#data8). it is generally used to access the external code or da ta space (e.g. movc a,@a+dptr or movx a, @dptr respectively). mnemonic: dpl address: 82h 7 6 5 4 3 2 1 0 reset dpl [7:0] 00h dpl[7:0]: data pointe r low mnemonic: dph address: 83h 7 6 5 4 3 2 1 0 reset dph [7:0] 00h dph [7:0]: data pointer high
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 19 - 5. gpio port 0 ~ port 3 are the general purpose io of this controller. most of the ports are multiplexed with the other outputs, e.g., port 3[0] is also used as rxd in the uart application. port0 is open - drain in the input and output high condition, so external pull - up resistors are required. as for the other ports, the pull - up resistors are built internally. for general purpose applications, ever y pin can be assigned to either high or low independently bec ause their sfrs are bit addressable as given below mnemonic: p0 address: 80h 7 6 5 4 3 2 1 0 reset p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh p0.7~ 0: port0 [7] ~ port0[0] mnemonic: p1 address: 90h 7 6 5 4 3 2 1 0 reset p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh p1.7~ 0: port1 [7] ~ port1 [0] mnemonic: p2 address: a0h 7 6 5 4 3 2 1 0 reset p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh p2. 7 ~ 0: port2 [ 7 ] ~ port2 [0] mnemonic: p 3 address: b0h 7 6 5 4 3 2 1 0 reset p3.7 p3.6 p3.5 p3. 4 p3.3 p3.2 p3.1 p3.0 ffh p 3 . 7 ~ 0: port 3 [ 7 ] ~ port 3 [0]
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 20 - 6. timer 0 and timer 1 the sm 5953 has three 16 - bit timer/counter registers: timer 0, timer 1 and timer 2. all can be configured for counter or timer operations. in timer mode, the timer 0 register or timer 1 register is incremented every machine cycles, d ue to 12 oscillator periods in a machine cycle, the count rate is 1/12 of the oscillator frequency. if in 6t mode, the count rate is 1/ 6 of the oscillator frequency . in counter mode, the r egister is incremented when the falling edge is observed at the corresponding input pin t0 or t1. since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special f unction registers (tmod and tcon) are used to select the a ppropriate mode. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst timer 0 and 1 tl0 timer 0 , low byte 8ah tl0[7:0] 00h th0 timer 0 , high byte 8ch th0[7:0] 00h tl1 timer 1 , low byte 8bh tl1[7:0] 00h th1 timer 1 , high b yte 8dh th1[7:0] 00h tmod timer mode control 89h gate c/t m1 m0 gate c/t m1 m0 00h tcon timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h 6.1 timer/counter mode control register (tmod) mnemonic: tmod address: 89h 7 6 5 4 3 2 1 0 reset gate c/ t m1 m0 gate c/t m1 m0 00h timer 1 timer 0 gate: if set, enables external gate control (pin int0 or int1 for counter 0 or 1, respectively). when int0 or int1 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge o n t0 or t1 input pin . c/t: selects timer or counter operation. when set to 1, a counter operation is performed, when cleared to 0, the corresponding register will function as a timer. m1 m0 mode function 0 0 mode0 13 - bit counter/timer, with 5 lower bits in tl0 or tl1 register and 8 bits in th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are hold at zero. 0 1 mode1 16 - bit counter/timer. 1 0 mode2 8 - bit auto - reload counter/timer. the reload value is kept i n th0 or th1, while tl0 or tl1 is incremented every machine cycle. when tlx overflows, a value from thx is copied to tlx.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 21 - 1 1 mode3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independ ent 8 bit timers / counters. 6.2 timer/counter control register (tcon) mnemonic: tcon address: 88h 7 6 5 4 3 2 1 0 reset tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tf1: timer 1 overflow flag set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr1: timer 1 run control bit. if cleared, timer 1 stops. tf0: timer 0 overflow flag set by hardware when timer 0 overflows. this flag can be cleared by software and is automatically clear ed when interrupt is processed. tr0: timer 0 run control bit. if cleared, timer 0 stops. ie1: interrupt 1 edge flag. set by hardware, when falling edge on external pin int1 is observed. cleared when interrupt is processed. it1: interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. it1=1, interrupt 1 select falling edge trigger. it1=0, interrupt1 select low level trigger. ie0: interrupt 0 edge flag. set by hardware, when falling edge on external pin int0 is obse rved. cleared when interrupt is processed. it0: interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. it0=1, interrupt 0 select falling edge trigger. it0=0, interrupt 0 select low level trigger. 6.3 mode 0 (13 - bit c ounter/timer) the timer register is configured as a 13 - bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfx. the counted input is enabled to the timer when trx = 1 and either gate=0 or intx = 1. mode 0 operatio n is the same for timer0 and timer1. fig. 6 - 1 : mode 0 - 13 bit timer / counter operation
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 22 - 6.4 mode 1 (16 - bit counter/timer) mode1 is the same as mode0, except that the timer register is being run with all 16 bits. fig. 6 - 2 : mode 1 16 bit counter/timer operation 6.5 mode 2 (8 - bit auto - reload counter/timer) mode 2 configures the timer register as an 8 - bit counter(tlx) with automatic reload. overflow from tlx not only set tfx, but also reload tlx with the co ntent of thx, which is determined by software. the reload leaves thx unchanged. mode 2 operation is the same for timer0 and timer1. fig. 6 - 3 : mode 2 8 - bit auto - reload counter/timer operation. 6.6 mode 3 (timer 0 acts as two ind ependent 8 bit timers / counters) timer1 in mode3 simply holds its count, the effect is the same as setting tr1 = 1. timer0 in mode 3 enables tl0 and th0 as two separate 8 - bit counters. tl0 uses the timer0 control bits such like c/t, gate, tr0, int0 and t f0. th0 is locked into a timer function (can not be external event counter) and take over the use of tr1, tf1 from timer1. th0 now controls the timer1 interrupt.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 23 - fig. 6 - 4 : mode 3 timer 0 acts as two independent 8 bit timers / counters operatin
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 24 - 7. timer 2 timer2 is a 16 - bit timer/counter which can operate as either an event timer or an event counter as selected by c/t2 in the special function register t2con. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst serial interface 0 and 1 tl2 timer 2 , low byte cch tl2[7:0] 00h th2 timer 2 , high byte cdh th2[7:0] 00h rcap2l reload and capture data low byte cah rcap2l[7:0] 00h rcap2h reload and capture data high byte cbh rcap2h[7:0] 00h t2mod timer 2 mo de c9h - - - - - - t2oe dcen x 0 h t2con timer 2 control register c8h tf2 exf2 rclk tclk exen 2 tr2 c/ t2 cp/ rl2 00h mnemonic: t2mod address: 98h 7 6 5 4 3 2 1 0 reset - - - - - - t2oe dcen 00h t2oe : timer 2 outp ut enable bit. it enables timer2 overflow rate to toggle p1.0. dcen : down count enable bit. when set, this allows timer2 to be configured as an up/down counter . mnemonic: t2con address: 98h 7 6 5 4 3 2 1 0 reset tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 00h tf2 : timer 2 overflow flag is set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. exf2 : timer 2 external flag is set when either a capture or rel oad is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter m ode (dcen = 1). rclk : receive clock enable. when set, causes the serial port to use timer 2 overflow pluses for its receive clock in serial port modes 1 and 3. rclk = 0 causes timer 1 overflows to be used for the receive clock. tclk : transmit clock enabl e. when set, causes the serial port to use timer 2 overflow pulses for it?s transmit clock in serial port modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 25 - exen2 : timer 2 external enable. when set, allows a capture or rel oad to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 : start/stop control for timer 2. tr2 = 1 starts the timer. c/ t2 : timer or counter select for timer 2. c/ t2 = 0 for timer function. c/ t2 = 1 for external event counter (falling edge triggered). cp/ rl2 : capture/reload select. cp/ rl2 = 1 cau ses captures to occur on negative transitions at t2ex if exen2 = 1. cp/ rl2 = 0 causes automatic reloads to occur when timer 2 overflows or negative transitions occur at t2ex when exen2 = 1. when either rclk or tclk = 1, this bit is igno red and the timer is forced to auto - reload on timer 2 overflow. table 7 - 1 : timer 2 operating modes rclk + tclk cp/rl2 tr2 dcen mode x x 0 x off 1 x 1 0 baud - rate generation 0 1 1 0 capture 0 0 1 0 auto - reload up - only 0 0 1 1 auto - reload up/down 7.1 c apture mode in the capture mode, there are two options selected by bit exen2 in t2con. if exen2 = 0, timer 2 is a 16 - bit timer or counter which upon overflow sets bit tf2 in t2con. this bit can then be used to generate an interrupt. if exen2 = 1, timer 2 s till does the above, but with the added feature that a 1 - to - 0 transition at external input t2ex causes the current value in th2 and tl2 to be captured into rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set. the exf2 bit, like tf2, can generate an interrupt. c/t2=0 c/t2=1 t2 pin tl2 (8 bits) th2 (8 bits) tf2 fosc/12 tr2 rcap2l rcap2h t2 ex pin exen2 exf2 transition detector timer2 interrupt timier2 in capture mode fig . 7 - 1 timer 2 in capture mode
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 26 - 7.2 auto - reload (up or down counter) timer 2 can be programmed to count up or down when configured in its 16 - bit auto - reload mode. this fea ture is invoked by a bit named dcen (down counter enable) located in the sfr t2mod. upon reset, the dcen bit is set to 0 so that timer 2 will default to count up. when dcen is set, timer 2 can count up or down depending on the value of the t2ex pin. fig . 7 - 2 shows timer 2 automatically counting up when dcen = 0. in this mode there are two options selected by bit exen2 in t2con. if exen2 = 0, timer 2 counts up to ffffh and then sets the tf2 bit upon overflow. the overflow also causes the timer registers to be reloaded with the 16 - bit value in rcap2h and rcap2l. the values in rcap2h and rcap2l are preset by software. if exen2 = 1, a 16 - bit reload can be triggered either by an overflow or by a 1 - to - 0 transition at external input t2ex. this transition also set s the exf2 bit. both the tf2 and exf2 bits can generate an interrupt if enabled. setting the dcen bit enables timer 2 to cou nt up or down as shown in fig . 7 - 3. in this mode the t2ex pin controls the direction of count. a logic 1 at t2ex makes timer 2 coun t up. the timer will overflow at ffffh and set the tf2 bit. this overflow also causes the 16 - bit value in rcap2h and rcap2l to be reloaded into the timer registers, th2 and tl2, respectively. a logic 0 at t2ex makes timer 2 count down. now the timer unde rflows when th2 and tl2 are equal to the values stored in rcap2h and rcap2l. the underflow sets the tf2 bit and causes ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows. this bit can be used as a 17th bit of resolution if desired. in this operating mode, exf2 does not flag an interrupt. c/t2=0 c/t2=1 t2 pin tl2 (8 bits) th2 (8 bits) tf2 fosc/12 tr2 rcap2l rcap2h t2 ex pin exen2 exf2 transition detector timer2 interrupt timier2 in auto reload mode (dcen=0) reload fig . 7 - 2 t imer 2 in auto reload mode (dcen=0)
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 27 - c/t2=0 c/t2=1 t2 pin tl2 th2 tf2 fosc/12 tr2 rcap2l rcap2h timier2 in auto reload mode (dcen=1) ffh ffh exf2 t2ex pin count direction 1 = up 0 = down timer2 interrupt fig . 7 - 3 timer 2 in auto reload mode (dcen=1) 7.3 programm able clock out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides begin a regular i/o pin, has two alternate functions. it can be programmed (1) to input the external clock for timer/counter 2 or (2) to output a 50% duty cycle clock. an example is that the clock output ranges from 61hz to 4mhz at a 16mhz oscillator frequency if in 12t mode. to configure the timer/counter 2 as a clock generator, bit c/ 2 t (t2con.1) must be cleared and bit t2oe(t2mod.1) must be set. bit tr2 (t2con.2) starts and stops the timer. the clock - out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: clock - out frequency = ) 2 , 2 65536 ( 4 frequency oscillator l rcap h rcap ? in the clock - out mode, timer 2 roll - overs will not generate an interrupt. this is similar to when timer 2 is used as a baud- rate generator. it is possible to use timer 2 as a baud - rate generator and a clock generator simultaneously. note, however, that th e baud - rate and clock - out frequencies can not be determined independently from one another since they both use rcap2h and rcap2l.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 28 - fig . 7 - 4 timer 2 in clock - out mode
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 29 - 8. serial interface ? uart the serial buffer consists of two separate r egisters, a transmit buffer and a receive buffer. writing data to the special function register sbuf sets this data in serial output buffer and starts the transmission . reading from the sbuf reads data from the serial receive buffer. the serial port can s imultaneously transmit and receive data. it can also buffer 1 byte at receive, which prevents the receive data from being lost if the cpu reads the first byte before transmission of the second byte is completed. mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst serial interface 0 and 1 pcon power control 87h smod - - - gf1 gf0 pd idle 00h scon serial port control register 98h sm 0 sm 1 sm 2 ren tb8 rb8 ti ri 00h sbuf serial port data buffer 99h sbuf[7:0] 00h mnemonic: scon ad dress: 98h 7 6 5 4 3 2 1 0 reset sm 0 sm 1 sm 2 ren tb8 rb8 ti ri 00h sm 0, sm 1: serial port 0 mode selection. sm 0 sm 1 mode 0 0 0 0 1 1 1 0 2 1 1 3 the 4 modes in uart, mode 0 ~ 3, are explained later. sm 2: enables multiprocessor communication featur e ren: if set, enables serial reception. cleared by software to disable reception. tb8: the 9th tran sm itted data bit in modes 2 and 3. set or cleared by the cpu depending on the function it performs such as parity check, multiprocessor communication etc . rb8: in modes 2 and 3, it is the 9th data bit received. in mode 1, if sm 2 is 0, rb8 is the stop bit. in mode 0, this bit is not used. must be cleared by software. ti: tran sm it interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software . ri : receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. 8.1 serial interface the serial interface can operate in the following 4 modes: sm 0 sm 1 mode description board rate 0 0 0 shift register fosc/12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fosc/32 or fosc/64 1 1 3 9 - bit uart variable
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 30 - here fosc is the crystal or oscillator frequency. the serial port of maryland is full duplex, can transmit and receive simultaneously. th e serial port receive and transmit share the same sfr ? sbuf, but actually there is two sbuf in the chip, one is for transmit and the other is for receive. the serial port can be operated in 4 different modes. 8.1.1 mode 0 pin rxd serves as input and output. txd outputs the shift clock. 8 bits are tran sm itted with lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in mode 0 by setting the flags in scon as follows: ri = 0 and ren = 1. in other modes, a start bit when ren = 1 starts receiving serial data. a s shown in fig. 8 - 1 and fig. 8 - 2 fig. 8 - 1 : tran sm it mode 0 fig. 8 - 2 : receive mode 0 8.1.2 mode 1 pin rxd serves as input, and txd serves as serial output. no external shift clock is used, 10 bits are tran sm itted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the tran sm i ssion, 8 data bits are available by reading sbuf, and stop bit sets the flag rb8 in the special function register scon. in mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate. a s shown in fig. 8 - 3 and fig. 8 - 4 fig. 8 - 3 : transmit mode 1
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 31 - fig. 8 - 4 : receive mode 1 8.1.3 mode 2 this mode is similar to mode 1, with two differences. the baud rate is fixed at 1/32 ( smod =1) or 1/64( smod =0) of oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable 9th bit, and a stop bit (1). the 9th bit can be used to control the parity of the seria l interface: at transmission , bit tb8 in scon is output as the 9th bit, and at receive, the 9th bit affects rb8 in special function register scon. 8.1.4 mode 3 the only difference between mode 2 and mode 3 is that in mode 3 either internal baud rate generator or timer 1 can be use to specify baud rate. a s shown in fig. 8 - 5 and fig. 8 - 6 . fig. 8 - 5 : transmit modes 2 and 3 fig. 8 - 6 : receive modes 2 and 3 8.2 multiprocessor communication of serial interface the feature of receiving 9 bits in modes 2 and 3 of serial interface can be used for multiprocessor communication. in this case, the slave processors have bit sm 2 in scon set to 1. when the master processor outputs slave?s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. the slave processors compare the received byte with their network address. if there is a match, the addressed sla ve will clear sm 2 and receive the rest of the message, while other slaves will leave sm 2 bit unaffected and ignore this message. after addressing the slave, the host will output the rest of the message with the 9th bit set to 0, so no serial port receive i nterrupt will be generated in unselected slaves.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 32 - 8.3 baud r ate g enerator 8.3.1 serial interface mode 0 baud rate = 12 fosc 8.3.2 serial interface mode 2 baud rate = 64 2 smod ( fosc ) 8.3.3 serial interface mode 1 and 3 8.3.3.1 using t imer 1 to generate baud rates. baud rate = 32 2 smod (timer 1 overflow rate) = ] 1 256 [ 12 fosc 32 2 th smod ? 8.3.3.2 using timer 2 to generate baud rates. baud rate = 32 rate overflow 2 timer = rcap2l)] (rcap2h, - [65536 32 fosc
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 33 - 9. interrupt the sm 5953 provides 6 interru pt sources with two priority levels. each source has its own request flag(s) located in a special function register. each interrupt requested by the corresponding flag could individually be enabled or disabled by the enabl e bits in sfr?s ie . when the inter rupt occurs, the engine will vector to the predetermined address as given in table 9 - 1 . once interrupt service has begun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminat ed by a return from instruction reti. when an reti is performed, the processor will return to the instruction that would have been next when interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by setting a flag bi t. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled once per machine cycle, and then samples are polled by hardware. if the sample indicates a pending interrupt when the interrupt is enabled, then i nterrupt request flag is set. on the next instruction cycle the interrupt will be acknowledged by hardware forcing an lcall to appropriate vector address. interrupt response will require a varying amount of time depending on the state of microcontroller wh en the interrupt occurs. if microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. in other cases, the response time depends on current instruction. table 9 - 1 : interrupt vectors priority level interrupt request flags interrupt vector address interrupt number *(use keil c tool) 1 (highest) ie0 ? external interrupt 0 0003h 0 2 tf0 ? timer 0 interrupt 000bh 1 3 ie1 ? external interrupt 1 0013h 2 4 tf1 ? ti mer 1 interrupt 001bh 3 5 ri0/ti 0 ? serial channel 0 interrupt 0023h 4 6 tf2/exf2 ? timer 2 interrupt 002bh 5 *see keil c about c51 user?s guide about interrupt function description mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst interrupt ie interrupt enable register a8h ea - et2 es et1 ex1 et0 ex0 00h ip interrupt priority register b8h - - pt2 ps pt1 px1 pt0 px0 00h mnemonic: ie address: a8h 7 6 5 4 3 2 1 0 reset ea - et2 es et1 ex1 et0 ex0 00h ea: ea=0 ? di sable all interrupt. ea=1 ? enable all interrupt. et2: et2=0 ? disable timer 2 overflow or external reload interrupt. et2=1 ? enable timer 2 overflow or external reload interrupt. es: es=0 ? disable serial channel interrupt. es=1 ? enable serial channel interrupt.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 34 - et1: et1=0 ? disable timer 1 overflow interrupt. et1=1 ? enable timer 1 overflow interrupt. ex1: ex1=0 ? disable external interrupt 1. ex1=1 ? enable external interrupt 1. et0: et0=0 ? disable timer 0 overflow interrupt. et0=1 ? enable timer 0 overflow interrupt. ex0: ex0=0 ? disable external interrupt 0. ex0=1 ? enable external interrupt 0. mnemonic: ip address: b8 h 7 6 5 4 3 2 1 0 reset - - pt2 ps pt1 px1 pt0 px0 00h pt2 : timer2 interrupt priority bit. ps : serial port interrupt prior ity bit. pt1 : timer1 interrupt priority bit. px1 : external interrupt 1 priority bit. pt0 : timer 0 interrupt priority bit. px0 : external interrupt 0 priority bit. interrupt priority table ip.x priority level 1 1 (highest) 0 2
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 35 - 10. watch dog time r the watch dog timer (wdt) is an 16- bit free - running counter that generate reset signal if the counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or ru naway. the wdt function can help user software recover from abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wd r bit of sconf register whenever un- predicted reset happened. after an external reset the watchdog timer is disabled and all registers are set to zeros. the wdt has selectable divider input for the time base source clock. to select the divider inpu t, the setting of bit 2 ~ bit0 ( ps[ 2 :0]) of watch dog timer control register (wdtc) should be set accordingly . as shown in table 10 - 1 . to enable the wdt is done by setting 1 to the bit 7 (wdte) of wdtc. after wdte set to 1, the 16 - bit counter starts to count with the selected time base source clock which set by ps2~ps0. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when sm 5953 been reset, either hardware reset or wdt reset. to reset the wdt is done by setting 1 to the bit 5 (clear) of wdtc. this will clear the content of the 16 - bit counter and let the counter re - start to count from the beginning. table 10- 1 : wdt time - out period ps[ 2 :0 ] divider (dividing of fosc) time period @ 40 m hz 000 8 13.1ms 001 16 26.21ms 010 32 52.42ms 011 64 104.8ms 100 128 209.71ms 101 256 419.43ms 110 512 838.86ms 111 1024 1677.72ms fosc 3 0] : ps[2 2 1 + wdtc ps[2:0] wdten enable/disable wdt wdt counter wdtclk clr refresh wdt counter 1. power on reset 2. external reset 3. software write ?0? wdr set wdr = 1 clear wdtf = 0 wdt time-out reset wdt time-out select fig. 10 - 1 : w atchdog timer block diagram
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 36 - mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst watchdog timer wdtc watchdog timer control register 9fh wdte - clear - - ps [2:0] 00h sconf system control register bfh wdr - - - - ispe - alei 00h mnemonic: wdtc address: 9fh 7 6 5 4 3 2 1 0 reset wdte - clear - - ps [2:0] 00h wdte: watch dog timer enable bit. clear: watch dog timer clear bit. if clear bit set to1, s etting this bit the watchdog timer counter clear and re - start to count fr om the beginning . ps [2:0] : watch d og timer over flow period setting. mnemonic: sconf address: bfh 7 6 5 4 3 2 1 0 reset wdr - - - - ispe - alei 00h wdr watch dog timer reset. when system reset by watch dog timer overflow, wdr will be set to 1. user should check wdr bit whenever un - predicted reset happened.
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 37 - 11. power management unit power management unit serves two power management modes, i dle and power down , for the users to do power saving function. mnemonic: pcon address: 87h 7 6 5 4 3 2 1 0 reset smod - - - gf1 gf0 pd idle 00h gf1 : general - purpose flag bit. gf0 : general - purpose flag bit. pd : power down mode control bit. setting this bit turning on the pd mode. pd bit is always read as 0 idle: idle mode control bit. setting this bit turning on the idle mode. idle bit is always read as 0 11.1 idle mode an instruction that sets pcon.0 causes that to be the last instruction executed before going into the idle mode, the internal clock is gated off to the cpu but not to the interrupt, tim er and serial port functions. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti, the next instruction to be executed will be the one following the instruction that put the device into idle. another way to wake - up from idle is to pull reset high to generate internal hardware reset. 11.2 power down mode an instruction that sets pcon.1 cause that to be the last inst ruction executed before going into the power - down mode. in the power - down mode, the on - chip oscillator is stopped. the contents of on - chip ram and sfrs are maintained. be carefully to keep reset pin active for at least 10ms in order for a stable clock. the power - down mode can be woken - up by reset pin. when it is woken - up by reset, the program will execute from the address 0000h. pin status in idle mode and p ower - d own mode mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data dat a data idle external 1 1 float data address data power - down internal 0 0 data data data data power - down external 0 0 float data data data
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 38 - 12. in - system programming (internal isp) the sm 5953 can generate flash control signal by internal hardware circuit . users utilize flash control register, flash address register and flash data register to perform the isp function without removing the sm 5953 from the system. the sm 5953 provides internal flash control signals which can do flash program/chip erase/page er ase/protect functions. user need to design and use any kind of interface which sm 5953 can input data. user then utilize isp service program to perform the flash program/chip erase/page erase/protect functions. 12.1 isp service program the isp service program i s a user developed firmware program which resides in the isp service program space. after user developed the isp service program, user then determine the size of the isp service program. user need to program the isp service program in the sm 5953 for the is p purpose. the isp service programs were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between sm 5953 and host device which output data to the sm 5953 . for example, if user utilize uart interface to receive/ t ransmit data between sm 5953 and host device, the isp service program should include baud rate, checksum or parity check or any error - checking mechanism to avoid data transmission error. 12.2 lock bit (n) the lock bit n has two functions: one is for service program size configuration and the other is to lock the isp service program space from flash erase function. the isp service program space address range $ 3 0 00 to $ 3 f 7 f. it can be divided as blocks of n. (n=0 to 8). when n=0 means no isp function . the maximum isp service program allowed is 3.875 k byte when n= 8 . the lock bit n function is different from the flash protect function. the flash erase function can erase all of the flash memory except for the locked isp service program space. if the flash not has been protected, the content of isp service program still can be read. if the flash has been protected, the overall content of flash program memory space including isp service program space can not be read. as given in table 12- 1 . table 12- 1 isp code area isp service program address 0 no isp service program 1 384 bytes ($ 3 e0 0h ~ $ 3 f 7 fh) 2 896 k bytes ($ 3 c 00h ~ $ 3 f 7 fh ) 3 1. 375 k bytes ($ 3 a0 0h ~ $ 3 f 7 fh ) 4 1.875 k bytes ($ 3 80 0h ~ $ 3 f 7 fh ) 5 2. 375 k bytes ($ 3 60 0h ~ $ 3 f 7 fh ) 6 2.875 k bytes ($ 3 4 00h ~ $ 3 f 7 fh ) 7 3. 375 k bytes ($ 3 20 0h ~ $ 3 f 7 fh ) 8 3.875 k bytes ($ 3 0 00h ~ $ 3 f 7 fh ) isp service program configurable in n (n= 0 ~ 8)
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 39 - 12.3 program the isp se rvice program after lock bit n is set and isp service program been programmed, the isp service program memory will be protected (locked) automatically. the lock bit n has its own program/erase timing. it is different from the flash memory program/erase tim ing so the locked isp service program can not be erased by flash erase function. if user needs to erase the locked isp service program, he can do it by writer only. user can not change isp service program when sm 5953 was in system. 12.4 initiate isp service pro gram to initiate the isp service program is to load the program counter (pc) with start address of isp service program and execute it. there are four ways to do so: (1) blank reset. hardware reset with first flash address blank ($0000=#ffh) will load the pc w ith start address of isp service program. (2) execute jump instruction can load the start address of the isp service program to pc. (3) reset is asserted with p2.6 and p2.7 both at low state. user can change enable or disable by writer. during the strobe window, the hardware will detect the status of p2.6 and p2.7 . if they meet one of above conditions, chip will switch to isp mode automatically. after isp service program executed, user need to reset the sm 5953 , either by hardware reset or by wdt, or jump to the a ddress $0000 to re - start the firmware program. 12.5 isp register ? ispfah, ispfal, ispfd and isp c mnemonic description dir. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst isp function ispfah isp flash address ? high register f4 h ispfah [7:0] 00h is pfal isp flash address - low register f5 h ispfal [7:0] 00h ispfd isp flash data register f6 h ispfd [7:0] 00h isp c isp control register f7h start - - - - - ispf[1:0] 00h mnemonic: ispfah address: f4 h 7 6 5 4 3 2 1 0 reset ispfah7 ispfah6 ispfah5 i spfah4 ispfah3 ispfah2 ispfah1 ispfah0 00 h ispfah [ 7 :0]: flash address - high for isp function
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 40 - mnemonic: ispfal address: f5 h 7 6 5 4 3 2 1 0 reset ispfal7 ispfal6 ispfal5 ispfal4 ispfal3 ispfal2 ispfal1 ispfal0 00 h ispfal [7:0]: flash address - low for isp function the ispfah & ispfal provide the 16- bit flash memory address for isp function. the flash memory address should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the isp service program space address, the flash program/page erase of isp function executed thereafter will have no effect. mnemonic: ispfd address: f6 h 7 6 5 4 3 2 1 0 reset ispfd7 ispfd6 ispfd5 ispfd4 ispfd3 ispfd2 ispfd1 ispfd0 00 h ispfd [7:0]: f lash data for isp function. the ispfd provide the 8 - bit data register for isp function. mnemonic: isp c address: f7 h 7 6 5 4 3 2 1 0 reset start - - - - - ispf[1:0] 00h start : isp function start bit = 1: start isp function which indicated by bit 1, bit 0 (ispf[1:0]) = 0: no operation ispf [1 :0]: isp function select bit. ispf[ 1 :0] isp function 00 byte program 01 chip protect 10 page erase 11 chip erase one page of flash memory is 128 byte the choice isp function will start to execute once th e software write data to isp c register. to perform byte program/page erases isp function, user need to specify flash address at first. when performing page erase function, sm 5953 will erase entire page which flash address indicated by ispfah & ispfal regis ters located within the page. e.g. flash address: $ xy 00 page erase function will erase from $xy00 to $xy 7 f to perform the chip erase isp function, sm 5953 will erase all the flash program memory except the isp service program space. to perform chip prote ct isp function, the sm 5953 flash memory content will be read #00h. the program will miss the interrupt if it happens during the isp funtion. e.g. isp service program to do the byte program - to program #22h to the address $1005h
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 41 - clr ea ;disable inte rrupt mov ispfd, #55h mov ispfd, #0aah mov ispfd, #5 5 h ; enable ispe write attribute orl s con f , #0 4 h ; enable isp function mov ispfah, #10h ; set flash address - high, 10h mov ispfal, #05h ; set flash address - low, 05h mov ispfd, #22h ; set flash data to be programmed, data = 22h mov isp c, # 8 0h ; start to program #22h to the flash address $1005h anl s con f , #0f b h ; disable isp function setb ea ; enable interrupt
s m5953 8 - bit micro - controller 15 kb with isp flash & 256 b ram embedded specifications subject to change without notice c ontact your sales representatives for the most recent information. i ssfd - m 074 ver d SM5953 0 4 / 16 /201 5 - 42 - operating conditions symbol description min. typ. max. un it. remarks ta operating temperature - 40 25 85 ambient temperature under bias vdd supply voltage 2. 4 5.5 v dc characteristics ta = - 40 to 85 , vcc = 5.0v symbol parameter valid min. max. unit test conditions vil1 input low voltage port 0,1,2,3, #ea - 0.5 0.8 v vil2 input low voltage res, xtal1 0 0.8 v vih1 input high voltage port 0,1,2,3,#ea 2.0 vcc+0.5 v vih2 input high voltage res, xtal1 70%vcc vcc+0.5 v vol1 output low voltage port 0, ale, #psen 0.45 v iol=3.2ma vol2 output low voltag e port 1,2,3, 0.45 v iol=1.6ma voh1 output high voltage port 0 2.4 v ioh= - 800ua 90%vcc v ioh= - 80ua voh2 output high voltage port 1,2,3,ale,#psen 2.4 v ioh= - 60ua 90%vcc v ioh= - 10ua iil logical 0 input current port 1,2,3 - 75 ua vin=0.45v it l logical transition current port 1,2,3 - 650 ua vin=2.0v ili input leakage current port 0, #ea 10 ua 0.45v

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